/* Automatically generated; edit at your own risk */

#define CONFIG_ARCH_AVR 1
#define CONFIG_AVR_3_BYTE_PC 1
#define CONFIG_AVR_ARCH 107
#define CONFIG_AVR_CORE 6
#define CONFIG_BOARD_XPLAIN 1
#define CONFIG_CHIP_ATXMEGA128A1 1
#define CONFIG_CPU_HZ 2000000UL
#define CONFIG_CPU_XMEGA 1
#define CONFIG_CSTACK_SIZE 0x100
#define CONFIG_DEBUG_DWARF2 1
#define CONFIG_EEPROM_END 0x7FF
#define CONFIG_EEPROM_SIZE 0x800
#define CONFIG_EEPROM_START 0x0
#define CONFIG_EXTRAM_BASE 0x800000
#define CONFIG_EXTRAM_END 0xFFFFFF
#define CONFIG_FLASH_END 0x21FFF
#define CONFIG_FLASH_NEND 0xFFFF
#define CONFIG_GC_SECTIONS 1
#define CONFIG_GENERIC_STRING_IMPL 1
#define CONFIG_HAVE_EBI 1
#define CONFIG_HAVE_HUGEMEM 1
//#define CONFIG_HAVE_HUGEMEM 0
#define CONFIG_HAVE_OSC 1
#define CONFIG_HAVE_PLL 1
#define CONFIG_HAVE_TC 1
#define CONFIG_INTLVL_AC0_COMP0 PMIC_INTLVL_LOW
#define CONFIG_INTLVL_AC0_COMP1 PMIC_INTLVL_LOW
#define CONFIG_INTLVL_AC0_WINDOW PMIC_INTLVL_LOW
#define CONFIG_INTLVL_AC1_COMP0 PMIC_INTLVL_LOW
#define CONFIG_INTLVL_AC1_COMP1 PMIC_INTLVL_LOW
#define CONFIG_INTLVL_AC1_WINDOW PMIC_INTLVL_LOW
#define CONFIG_INTLVL_ADC0_CH0 PMIC_INTLVL_LOW
#define CONFIG_INTLVL_ADC0_CH1 PMIC_INTLVL_LOW
#define CONFIG_INTLVL_ADC0_CH2 PMIC_INTLVL_LOW
#define CONFIG_INTLVL_ADC0_CH3 PMIC_INTLVL_LOW
#define CONFIG_INTLVL_ADC1_CH0 PMIC_INTLVL_LOW
#define CONFIG_INTLVL_ADC1_CH1 PMIC_INTLVL_LOW
#define CONFIG_INTLVL_ADC1_CH2 PMIC_INTLVL_LOW
#define CONFIG_INTLVL_ADC1_CH3 PMIC_INTLVL_LOW
#define CONFIG_INTLVL_AES_INT PMIC_INTLVL_LOW
#define CONFIG_INTLVL_DMA_INT PMIC_INTLVL_LOW
#define CONFIG_INTLVL_NVM_EE PMIC_INTLVL_LOW
#define CONFIG_INTLVL_NVM_SPM PMIC_INTLVL_LOW
#define CONFIG_INTLVL_OSCF_INT PMIC_INTLVL_LOW
#define CONFIG_INTLVL_PORTA_INT0 PMIC_INTLVL_LOW
#define CONFIG_INTLVL_PORTA_INT1 PMIC_INTLVL_LOW
#define CONFIG_INTLVL_PORTB_INT0 PMIC_INTLVL_LOW
#define CONFIG_INTLVL_PORTB_INT1 PMIC_INTLVL_LOW
#define CONFIG_INTLVL_PORTC_INT0 PMIC_INTLVL_LOW
#define CONFIG_INTLVL_PORTC_INT1 PMIC_INTLVL_LOW
#define CONFIG_INTLVL_PORTD_INT0 PMIC_INTLVL_LOW
#define CONFIG_INTLVL_PORTD_INT1 PMIC_INTLVL_LOW
#define CONFIG_INTLVL_PORTE_INT0 PMIC_INTLVL_LOW
#define CONFIG_INTLVL_PORTE_INT1 PMIC_INTLVL_LOW
#define CONFIG_INTLVL_PORTF_INT0 PMIC_INTLVL_LOW
#define CONFIG_INTLVL_PORTF_INT1 PMIC_INTLVL_LOW
#define CONFIG_INTLVL_PORTH_INT0 PMIC_INTLVL_LOW
#define CONFIG_INTLVL_PORTH_INT1 PMIC_INTLVL_LOW
#define CONFIG_INTLVL_PORTJ_INT0 PMIC_INTLVL_LOW
#define CONFIG_INTLVL_PORTJ_INT1 PMIC_INTLVL_LOW
#define CONFIG_INTLVL_PORTK_INT0 PMIC_INTLVL_LOW
#define CONFIG_INTLVL_PORTK_INT1 PMIC_INTLVL_LOW
#define CONFIG_INTLVL_PORTQ_INT0 PMIC_INTLVL_LOW
#define CONFIG_INTLVL_PORTQ_INT1 PMIC_INTLVL_LOW
#define CONFIG_INTLVL_PORTR_INT0 PMIC_INTLVL_LOW
#define CONFIG_INTLVL_PORTR_INT1 PMIC_INTLVL_LOW
#define CONFIG_INTLVL_RTC_COMP PMIC_INTLVL_LOW
#define CONFIG_INTLVL_RTC_OVF PMIC_INTLVL_LOW
#define CONFIG_INTLVL_SPI0 PMIC_INTLVL_LOW
#define CONFIG_INTLVL_SPI1 PMIC_INTLVL_LOW
#define CONFIG_INTLVL_SPI2 PMIC_INTLVL_LOW
#define CONFIG_INTLVL_SPI3 PMIC_INTLVL_LOW
#define CONFIG_INTLVL_TC0_CCA PMIC_INTLVL_LOW
#define CONFIG_INTLVL_TC0_CCB PMIC_INTLVL_LOW
#define CONFIG_INTLVL_TC0_CCC PMIC_INTLVL_LOW
#define CONFIG_INTLVL_TC0_CCD PMIC_INTLVL_LOW
#define CONFIG_INTLVL_TC0_ERR PMIC_INTLVL_LOW
#define CONFIG_INTLVL_TC0_OVF PMIC_INTLVL_LOW
#define CONFIG_INTLVL_TC1_CCA PMIC_INTLVL_LOW
#define CONFIG_INTLVL_TC1_CCB PMIC_INTLVL_LOW
#define CONFIG_INTLVL_TC1_ERR PMIC_INTLVL_LOW
#define CONFIG_INTLVL_TC1_OVF PMIC_INTLVL_LOW
#define CONFIG_INTLVL_TC2_CCA PMIC_INTLVL_LOW
#define CONFIG_INTLVL_TC2_CCB PMIC_INTLVL_LOW
#define CONFIG_INTLVL_TC2_CCC PMIC_INTLVL_LOW
#define CONFIG_INTLVL_TC2_CCD PMIC_INTLVL_LOW
#define CONFIG_INTLVL_TC2_ERR PMIC_INTLVL_LOW
#define CONFIG_INTLVL_TC2_OVF PMIC_INTLVL_LOW
#define CONFIG_INTLVL_TC3_CCA PMIC_INTLVL_LOW
#define CONFIG_INTLVL_TC3_CCB PMIC_INTLVL_LOW
#define CONFIG_INTLVL_TC3_ERR PMIC_INTLVL_LOW
#define CONFIG_INTLVL_TC3_OVF PMIC_INTLVL_LOW
#define CONFIG_INTLVL_TC4_CCA PMIC_INTLVL_LOW
#define CONFIG_INTLVL_TC4_CCB PMIC_INTLVL_LOW
#define CONFIG_INTLVL_TC4_CCC PMIC_INTLVL_LOW
#define CONFIG_INTLVL_TC4_CCD PMIC_INTLVL_LOW
#define CONFIG_INTLVL_TC4_ERR PMIC_INTLVL_LOW
#define CONFIG_INTLVL_TC4_OVF PMIC_INTLVL_LOW
#define CONFIG_INTLVL_TC5_CCA PMIC_INTLVL_LOW
#define CONFIG_INTLVL_TC5_CCB PMIC_INTLVL_LOW
#define CONFIG_INTLVL_TC5_ERR PMIC_INTLVL_LOW
#define CONFIG_INTLVL_TC5_OVF PMIC_INTLVL_LOW
#define CONFIG_INTLVL_TC6_CCA PMIC_INTLVL_LOW
#define CONFIG_INTLVL_TC6_CCB PMIC_INTLVL_LOW
#define CONFIG_INTLVL_TC6_CCC PMIC_INTLVL_LOW
#define CONFIG_INTLVL_TC6_CCD PMIC_INTLVL_LOW
#define CONFIG_INTLVL_TC6_ERR PMIC_INTLVL_LOW
#define CONFIG_INTLVL_TC6_OVF PMIC_INTLVL_LOW
#define CONFIG_INTLVL_TC7_CCA PMIC_INTLVL_LOW
#define CONFIG_INTLVL_TC7_CCB PMIC_INTLVL_LOW
#define CONFIG_INTLVL_TC7_ERR PMIC_INTLVL_LOW
#define CONFIG_INTLVL_TC7_OVF PMIC_INTLVL_LOW
#define CONFIG_INTLVL_TWI0_MASTER PMIC_INTLVL_LOW
#define CONFIG_INTLVL_TWI0_SLAVE PMIC_INTLVL_LOW
#define CONFIG_INTLVL_TWI1_MASTER PMIC_INTLVL_LOW
#define CONFIG_INTLVL_TWI1_SLAVE PMIC_INTLVL_LOW
#define CONFIG_INTLVL_TWI2_MASTER PMIC_INTLVL_LOW
#define CONFIG_INTLVL_TWI2_SLAVE PMIC_INTLVL_LOW
#define CONFIG_INTLVL_TWI3_MASTER PMIC_INTLVL_LOW
#define CONFIG_INTLVL_TWI3_SLAVE PMIC_INTLVL_LOW
#define CONFIG_INTLVL_USART0_DRE PMIC_INTLVL_LOW
#define CONFIG_INTLVL_USART0_RXC PMIC_INTLVL_LOW
#define CONFIG_INTLVL_USART0_TXC PMIC_INTLVL_LOW
#define CONFIG_INTLVL_USART1_DRE PMIC_INTLVL_LOW
#define CONFIG_INTLVL_USART1_RXC PMIC_INTLVL_LOW
#define CONFIG_INTLVL_USART1_TXC PMIC_INTLVL_LOW
#define CONFIG_INTLVL_USART2_DRE PMIC_INTLVL_LOW
#define CONFIG_INTLVL_USART2_RXC PMIC_INTLVL_LOW
#define CONFIG_INTLVL_USART2_TXC PMIC_INTLVL_LOW
#define CONFIG_INTLVL_USART3_DRE PMIC_INTLVL_LOW
#define CONFIG_INTLVL_USART3_RXC PMIC_INTLVL_LOW
#define CONFIG_INTLVL_USART3_TXC PMIC_INTLVL_LOW
#define CONFIG_INTLVL_USART4_DRE PMIC_INTLVL_LOW
#define CONFIG_INTLVL_USART4_RXC PMIC_INTLVL_LOW
#define CONFIG_INTLVL_USART4_TXC PMIC_INTLVL_LOW
#define CONFIG_INTLVL_USART5_DRE PMIC_INTLVL_LOW
#define CONFIG_INTLVL_USART5_RXC PMIC_INTLVL_LOW
#define CONFIG_INTLVL_USART5_TXC PMIC_INTLVL_LOW
#define CONFIG_INTLVL_USART6_DRE PMIC_INTLVL_LOW
#define CONFIG_INTLVL_USART6_RXC PMIC_INTLVL_LOW
#define CONFIG_INTLVL_USART6_TXC PMIC_INTLVL_LOW
#define CONFIG_INTLVL_USART7_DRE PMIC_INTLVL_LOW
#define CONFIG_INTLVL_USART7_RXC PMIC_INTLVL_LOW
#define CONFIG_INTLVL_USART7_TXC PMIC_INTLVL_LOW
#define CONFIG_INTLVL_USB_BUSEVENT PMIC_INTLVL_HIGH
#define CONFIG_INTLVL_USB_TRNCOMPL PMIC_INTLVL_HIGH
#define CONFIG_MEMORY_MODEL_LARGE 1
//#define CONFIG_MEMORY_MODEL_LARGE 0
#define CONFIG_NR_IRQS 125
#define CONFIG_OPTIMIZE_LEVEL 3
#define CONFIG_OPTIMIZE_SIZE 1
#define CONFIG_PORT_GPIO 1
#define CONFIG_PROG_PORT /dev/ttyUSB0
#define CONFIG_PROGRAMMER jtagicemkii
#define CONFIG_RELAX 1
#define CONFIG_RSTACK_SIZE 0x80
#define CONFIG_SERIAL_UART 1
#define CONFIG_SRAM_BASE 0x2000
#define CONFIG_SRAM_END 0x3FFF
#define CONFIG_SRAM_TBASE 0x0
#define CONFIG_SRAM_TSIZE 0x0
#define CONFIG_SYSCLK_PSADIV XMEGA_CLK_PSADIV_1
#define CONFIG_SYSCLK_PSBCDIV XMEGA_CLK_PSBCDIV_1_1
#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_RC2MHZ
#define CONFIG_UART_BAUD_RATE 9600
#define CONFIG_UART_CTRL 1
#define CONFIG_UART_ID 0
